1. Field of the Invention
This invention is related to the field of computer systems and, more particularly, to verifying synchronous links within computer systems.
2. Description of the Related Art
Integrated circuits (or “chips”) have included built-in self test (BIST) circuitry in order to ensure that the internal circuits of the chips are functioning properly. Generally, the BIST applies a series of test vectors to the inputs of the internal circuits and compares the outputs of the internal circuits to expected results. If the outputs differ from the expected results, then the BIST fails and the chip may include a faulty internal circuit. is BIST may be run on the chip at the time of manufacture of the integrated circuit to screen out faulty parts before delivery to a customer, and may be run when the system including the chip is powered up (or at some other time as may be desired) to ensure that the chip is still functioning properly. The interconnect between chips has typically been synchronous, and has typically not been tested using any type of BIST. In a synchronous interconnect, a single system clock is used by each of the chips connected to the synchronous interconnect to time the driving of signals on the interconnect and the sampling of signals from the interconnect. Each chip is designed to meet certain timing criteria with respect to the clock signal (e.g. setup and hold times), and these timing criteria may be tested for each chip when that chip is manufactured. However, once the chips are assembled into a system, the testing of the interconnect is typically limited to in-circuit testing (ICT) or boundary scan testing (e.g. the type of tests specified by IEEE 1149 and 1149.1). ICT and boundary scan testing is typically performed at low clock frequencies, generally significantly lower than the operating frequency of the interconnect (i.e. the frequency at which the interconnect operates when the system is running). Accordingly, ICT and/or boundary scan testing may detect faults such as broken connections in the interconnect but may be severely limited in detecting timing-related failures.
Generally, systems utilizing IBIST as described above include additional circuitry to generate test patterns and check test patterns. Because of the ever shrinking nature of modern electronics, it is desired that any additional circuitry be as efficient as possible.